This is quite close to your hardware description (clk_enable needs to be a reg here). Now we take care of the correct selection with plain combinational logic: always begin And you spare the counter logic (increments and comparison). I also included reset signals on negative edge, which you usually need. So this plain sequential logic takes care of generating the divided CLK signals of f/2 and f/4 that you need. You just want to assign the correct CLK signal to the output CLK.Īn implementation of the sequential part could look like: // frequency division from input CLK -> frequency: f/2 Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. However, the actual selection of the correct CLK output signal can be combinational. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter. So triggering on a CLK edge is really necessary here. This part needs to be sequential, since you want to invert the previous CLK state.this would cause a cmobinational loop if realized in combinational logic. This includes some thoughts on what part of the design actually has to be sequential and what can be combinational.įor your case, the clock division clearly has to be sequential, since you want to invert the generated CLK signal (frequency f/2, case 0'b01) at each positive edge of the incoming CLK signal (frequency f, case 0'b00). My suggestion is that you always make a clean cut between combinational and sequential logic.
CLOCK DIVIDER MUX VERILOG SOFTWARE
This looks like you have a strong background in software development? :) I am asking a help for the enabler=00 situation. I managed to divide my input clock for different cases with using case keyword but for enabler=00 my input clock should be equal to my output clk_enable which i could not manage to do it. If enabler=01 then my input clock should be enabled once in 2 clock signals.If enabler=10 then my input should be divided by 4 etc. I have a enabler input and an input clock, and an output named clk_enable.
I am asked to design simple clock divider circuit for different types of inputs.
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